TY - JOUR
T1 - Fama
T2 - An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design
AU - Xu, Yan
AU - Zhang, Jingqi
AU - Dong, Xiyan
AU - Wang, An
AU - Wang, Xinghua
AU - Zhu, Liehuang
N1 - Publisher Copyright:
© 1982-2012 IEEE.
PY - 2026/4/1
Y1 - 2026/4/1
N2 - Multiscalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof (ZKP) protocols. To address this, we introduce Fama, a field-programmable gate array (FPGA)-oriented MSM accelerator developed through algorithm-hardware co-optimization. By integrating a 3D-Pippenger optimization algorithm, Fama minimizes computational complexity, while its compact dual-mode point addition (PADD) unit significantly reduces hardware overhead. Compared to the best CPU-based design, Fama achieves over 184.20× speedup. It also outperforms state-of-the-art FPGA-based MSM accelerators, reducing resource overhead by more than 64% and boosting area-time product (ATP) by up to 37.09×.
AB - Multiscalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof (ZKP) protocols. To address this, we introduce Fama, a field-programmable gate array (FPGA)-oriented MSM accelerator developed through algorithm-hardware co-optimization. By integrating a 3D-Pippenger optimization algorithm, Fama minimizes computational complexity, while its compact dual-mode point addition (PADD) unit significantly reduces hardware overhead. Compared to the best CPU-based design, Fama achieves over 184.20× speedup. It also outperforms state-of-the-art FPGA-based MSM accelerators, reducing resource overhead by more than 64% and boosting area-time product (ATP) by up to 37.09×.
KW - Field-programmable gate array (FPGA)
KW - hardware accelerator
KW - multiscalar multiplication (MSM)
KW - zero-knowledge proof (ZKP)
UR - https://www.scopus.com/pages/publications/105015714662
U2 - 10.1109/TCAD.2025.3608005
DO - 10.1109/TCAD.2025.3608005
M3 - Article
AN - SCOPUS:105015714662
SN - 0278-0070
VL - 45
SP - 1867
EP - 1871
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 4
ER -