Estimation and calibration for channel mismatches in high-speed ADC systems

Since high-speed and high-resolution ADCs are needed in communication systems, single ADC can hardly achieve. This paper proposed a timing mismatch estimation and calibration algorithm in Time-Interleaved ADC (TIADC). A multistage differentiator-multiplier cascade (DMC) structure is disclosed for timing mismatch correction. As the present estimation and calibration method, the procedure can be performed without knowing input signal, and converges with smaller data samples. Finally, numerical simulations show that the proposed method can get good performance and Spurious Free Dynamic Range (SFDR) is improved significantly. The entire system can achieve 8 GHz and 8-bit resolution.