TY - GEN
T1 - Design of SINS/GPS integrated navigation system based on dual NiosII soft-core
AU - Chai, Zhi
AU - Miao, Lingjuan
AU - Shen, Jun
PY - 2012
Y1 - 2012
N2 - As an advanced integrated navigation system with excellent performance, the SINS/GPS system combines the advantages of strap-down inertial navigation system (SINS) and global positioning system (GPS) respectively. A new architecture of the SINS/GPS system is implemented on SOPC platform with dual NiosII soft-core, which is proposed as an alternative of the conventional implementation with FPGA plus DSP. The two NiosII soft-core, One CPU core is utilized for the central control, data acquisition and off-chip communication with the host computer, another core is for the implementation of real-time navigation. Moreover, the Kaiman filter is implemented as a specific IP embedded into the on-chip system, which possesses a higher efficiency than the conventional method by using C program on DSP. As a hardware filter, it's independent of NiosII. The experimental results show both excellent efficiency and real-time quality of the implemented system. Consequently, the proposed architecture with conspicuous advantages is more feasible and has a reduced resource usage, compared with the conventional method.
AB - As an advanced integrated navigation system with excellent performance, the SINS/GPS system combines the advantages of strap-down inertial navigation system (SINS) and global positioning system (GPS) respectively. A new architecture of the SINS/GPS system is implemented on SOPC platform with dual NiosII soft-core, which is proposed as an alternative of the conventional implementation with FPGA plus DSP. The two NiosII soft-core, One CPU core is utilized for the central control, data acquisition and off-chip communication with the host computer, another core is for the implementation of real-time navigation. Moreover, the Kaiman filter is implemented as a specific IP embedded into the on-chip system, which possesses a higher efficiency than the conventional method by using C program on DSP. As a hardware filter, it's independent of NiosII. The experimental results show both excellent efficiency and real-time quality of the implemented system. Consequently, the proposed architecture with conspicuous advantages is more feasible and has a reduced resource usage, compared with the conventional method.
UR - https://www.scopus.com/pages/publications/84874632169
U2 - 10.1109/ICACI.2012.6463151
DO - 10.1109/ICACI.2012.6463151
M3 - Conference contribution
AN - SCOPUS:84874632169
SN - 9781467317436
T3 - 2012 IEEE 5th International Conference on Advanced Computational Intelligence, ICACI 2012
SP - 198
EP - 202
BT - 2012 IEEE 5th International Conference on Advanced Computational Intelligence, ICACI 2012
T2 - 2012 IEEE 5th International Conference on Advanced Computational Intelligence, ICACI 2012
Y2 - 18 October 2012 through 20 October 2012
ER -