Design of AB² in Galois Fields Based on Multiple-Valued Logic

A new AB² operation in Galois Field GF(2⁴) is presented and its systolic realization based on multiple-valued logic (MVL) is proposed. The systolic structure of the operation employs multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL) to reduce the transistor and wire counts, and the initial delay. The performance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. A comparison is conducted between our proposed implementation and those reported in the literature. The transistor counts, the wire counts and the initial delay in our MVL design show savings of about 23%, 45%, and 72%, in comparison with the corresponding binary CMOS implementation. The systolic architecture proposed is simple, regular, and modular, well suited for very large scale integration (VLSI) implementation. The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF (2^k).