Design of a large point FFT processor with configurable transform length

Yu Xie; Yang Kai Feng; Chen Yang; Yi Zhuang Xie; He Chen

Design of a large point FFT processor with configurable transform length

Yu Xie
, Yang Kai Feng
, Chen Yang
, Yi Zhuang Xie^*
, He Chen

^*此作品的通讯作者

信息与电子学院

Beijing Institute of Technology

科研成果: 会议稿件 › 论文 › 同行评审

3 引用（Scopus）

摘要

In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16∼128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.

源语言	英语
出版状态	已出版 - 2015
活动	IET International Radar Conference 2015 - Hangzhou, 中国期限: 14 10月 2015 → 16 10月 2015

会议

会议	IET International Radar Conference 2015
国家/地区	中国
市	Hangzhou
时期	14/10/15 → 16/10/15

其它文件与链接

链接到 Scopus 的出版物

引用此

@conference{3dc13ed53e024d2dab44d0e70b07a36e,

title = "Design of a large point FFT processor with configurable transform length",

abstract = "In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16∼128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.",

keywords = "Configurable, FFT, FPGA, Large point, Real-time",

author = "Yu Xie and Feng, \{Yang Kai\} and Chen Yang and Xie, \{Yi Zhuang\} and He Chen",

year = "2015",

language = "English",

note = "IET International Radar Conference 2015 ; Conference date: 14-10-2015 Through 16-10-2015",

}

TY - CONF

T1 - Design of a large point FFT processor with configurable transform length

AU - Xie, Yu

AU - Feng, Yang Kai

AU - Yang, Chen

AU - Xie, Yi Zhuang

AU - Chen, He

PY - 2015

Y1 - 2015

N2 - In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16∼128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.

AB - In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16∼128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.

KW - Configurable

KW - FFT

KW - FPGA

KW - Large point

KW - Real-time

UR - https://www.scopus.com/pages/publications/84973567134

M3 - Paper

AN - SCOPUS:84973567134

T2 - IET International Radar Conference 2015

Y2 - 14 October 2015 through 16 October 2015

ER -

Design of a large point FFT processor with configurable transform length

摘要

会议

其它文件与链接

学术指纹

引用此