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Design and optimization of dual modulus prescaler using the extended true-single-phase-clock

  • Chao Guo*
  • , Siheng Zhu
  • , Jun Hu
  • , Jing Diao
  • , Houjun Sun
  • , Xin Lv
  • *此作品的通讯作者
  • Beijing Institute of Technology

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

摘要

A low-power divide-by-4/5 unit of a prescaler is proposed. The power consumption and operating frequency of the extended true-single-phase-clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are analyzed. Compared with the existing design, a 20% reduction of power consumption is achieved. A divide-by-16/17 dual-modulus prescaler implemented with this divide-by-4/5 unit using a 0.18-um CMOS process is capable of operating up to 4.1 GHz with a low-power comsumpti-on. The prescaler is implemented in low-power high-resolution frequency dividers for wireless short distance application.

源语言英语
主期刊名2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010
出版商IEEE Computer Society
页636-638
页数3
ISBN(印刷版)9781424457052
DOI
出版状态已出版 - 2010
已对外发布是

丛书

姓名2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010

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