Comprehensive Evaluation and Optimization of Level Count for Cascaded H-Bridge Multilevel Inverters with Carrier-Phase-Shifted PWM

Cascaded H-bridge (CHB) multilevel inverters are pivotal in high-power applications, such as renewable energy subsystems and motor drives, due to their superior modularity and harmonic performance. However, selecting the optimal number of levels remains a complex engineering trade-off between power quality, switching losses, and system complexity. This study presents a systematic investigation into CHB inverters ranging from three to twenty-one levels under carrier-phase-shifted sinusoidal pulse width modulation (CPS-SPWM) control. A detailed MATLAB/Simulink framework in version R2023a was established, incorporating a zero-order hold (ZOH) data synchronization protocol and parameterized macro-model MOSFETs to accurately quantify total harmonic distortion (THD) and individual switching energy dissipation. To evaluate the efficiency–quality equilibrium, a novel comprehensive evaluation index, the performance-to-loss ratio (PLR), is proposed. Simulation results indicate that while THD improves significantly with higher level counts, the marginal gains diminish beyond the 13-level configuration. Utilizing the PLR framework, the nine-level configuration is identified as a local optimum for cost-sensitive modularity, whereas the twenty-one-level setup provides the global optimum for high-performance scenarios where spectral purity is paramount. Accordingly, this proof-of-concept study provides a quantitative roadmap for designers and experimentalists to navigate the complex design space of multilevel inverters, enabling optimal allocation of hardware resources toward the net-zero vision while guiding future experimental efforts away from costly, exhaustive hardware characterization.