Analysis and Modeling of Error Propagation in Approximate FFT Processors

To reduce energy consumption in FFT accelerators while preserving acceptable accuracy, approximate computing has emerged as a viable design approach. This paper presents a quantitative error propagation model for FFT systems with approximate adders. By deriving analytical expressions of error evolution across butterfly stages, we establish a scalable and interpretable framework that supports approximation-aware hardware design. The model's validity is verified through comprehensive simulations and Vivado-based hardware implementations using multiple approximation strategies, including Trunc, CopyA, CopyB, and LOA. Among them, the Trunc1 strategy consistently demonstrates the lowest error across varying configurations. Experimental results show strong alignment between the theoretical predictions and actual outputs, confirming the model's cross-scale generalization. The proposed model eliminates the need for redundant empirical tuning and provides theoretical guidance for developing power-efficient FFT architectures under constrained resources.