An improved two-stage acquisition system and its VLSI implementation

It is known that normal two-stage acquisition algorithm is made up of matching filter as the front-end and serial sliding correlators as the back-end, which has the disadvantage of too much resource consumption. This paper proposes an improved two-stage acquisition system. The system is made up of a sliding correlator with short integration time as the front-end to skip the synchronization stage quickly and a bank of serial correlators with different integration time as the back-end for verification. Furthermore, an improved 1+M/N search detector algorithm is used in the system. At last, the acquisition circuit is implemented based on FPGA+DSP and proves the correctness of circuit modulus is proved by simulation of Modelsim. Comparative results show that the proposed system can reduce the resource consumption effectively and improve the detection probability dramatically.