TY - GEN
T1 - An Electrical Thermal Co-transmission (ETC) TSV Interconnect with Annular Cu Conductor and CNT Core for Improving the Thermal Management of Heterogeneous Chiplet Integration
AU - Zhang, Ziyue
AU - Wang, Han
AU - Hao, Yigang
AU - Su, Yuwen
AU - Chen, Xuyan
AU - Zhang, Jiaxuan
AU - Ding, Yingtao
AU - Chen, Zhiming
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - The heterogeneous integration (HI) of chiplets with various functionalities is an effective approach for realizing "More than Moore". However, thermal management presents a significant challenge for high-density integrated systems, especially those containing high-performance and high-power chiplets. In this work, we demonstrate a novel electrical thermal co-transmission (ETC) TSV structure featuring an annular Cu conductor and central CNT core, which not only serves as a vertical electrical interconnect but also provides enhanced heat dissipation between layers. The ETC TSVs are fabricated through a simplified process flow based on double-sided processes. Benefiting from the thick parylene liner, the TSVs exhibit excellent electrical performance characterized by low and stable parasitic capacitance, low leakage current, and low resistance. Furthermore, heat conduction measurements verify the capability of the ETC TSVs to enhance heat dissipation, thereby validating their effectiveness in improving the thermal management of high-density integrated systems.
AB - The heterogeneous integration (HI) of chiplets with various functionalities is an effective approach for realizing "More than Moore". However, thermal management presents a significant challenge for high-density integrated systems, especially those containing high-performance and high-power chiplets. In this work, we demonstrate a novel electrical thermal co-transmission (ETC) TSV structure featuring an annular Cu conductor and central CNT core, which not only serves as a vertical electrical interconnect but also provides enhanced heat dissipation between layers. The ETC TSVs are fabricated through a simplified process flow based on double-sided processes. Benefiting from the thick parylene liner, the TSVs exhibit excellent electrical performance characterized by low and stable parasitic capacitance, low leakage current, and low resistance. Furthermore, heat conduction measurements verify the capability of the ETC TSVs to enhance heat dissipation, thereby validating their effectiveness in improving the thermal management of high-density integrated systems.
UR - https://www.scopus.com/pages/publications/105033607403
U2 - 10.1109/IEDM50572.2025.11353487
DO - 10.1109/IEDM50572.2025.11353487
M3 - Conference contribution
AN - SCOPUS:105033607403
T3 - Technical Digest - International Electron Devices Meeting, IEDM
BT - 2025 IEEE International Electron Devices Meeting, IEDM 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE International Electron Devices Meeting, IEDM 2025
Y2 - 6 December 2025 through 10 December 2025
ER -