@inproceedings{320af38dfe2b479d96f462cba56596e9,
title = "An Automated Fault Injection Platform for Fault Tolerant FFT Implemented in SRAM-Based FPGA",
abstract = "Soft errors caused by Single Event Upset (SEU) has become a significant threat to modern electronic systems. Aiming at reliability evaluation of fault tolerant very large scale integrated circuits implemented on SRAM-based FPGA, an automated fault injection platform via Internal Configuration Access Port (ICAP) for rapid fault injection is presented in this paper. We adopt a fault tolerant FFT processor as the Design Under Test (DUT), and a C++ application is deployed for the external fault injection control environment and automating the fault injection procedure. The proposed method can achieve quantities of repeating fault injection tests and is suitable for any fault tolerant design implemented in SRAM-Based FPGA. In this paper, we through a large number of experiments to find the critical bit which can support fault tolerant of FFT processor.",
keywords = "Fast Fourier Transform (FFT), Fault Injection, Fault Tolerant(FT), SRAM-based FPGA, Single Event Upset(SEU)",
author = "Mao, \{Chuang An\} and Yu Xie and Yizhuang Xie and He Chen and Hao Shi",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 31st IEEE International System on Chip Conference, SOCC 2018 ; Conference date: 04-09-2018 Through 07-09-2018",
year = "2018",
month = jul,
day = "2",
doi = "10.1109/SOCC.2018.8618524",
language = "English",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "7--12",
editor = "Mircea Stan and Karan Bhatia and Helen Li and Massimo Alioto and Ramalingam Sridhar",
booktitle = "Proceedings - 31st IEEE International System on Chip Conference, SOCC 2018",
address = "United States",
}