@inproceedings{6bd619d440c84cb198dd841d84fb16fe,
title = "An acceleration system for Laplacian image fusion based on SoC",
abstract = "Based on the analysis of Laplacian image fusion algorithm, this paper proposes a partial pipelining and modular processing architecture, and a SoC based acceleration system is implemented accordingly. Full pipelining method is used for the design of each module, and modules in series form the partial pipelining with unified data formation, which is easy for management and reuse. Integrated with ARM processor, DMA and embedded bare-mental program, this system achieves 4 layers of Laplacian pyramid on the Zynq-7000 board. Experiments show that, with small resources consumption, a couple of 256×256 images can be fused within 1ms, maintaining a fine fusion effect at the same time.",
keywords = "FPGA acceleration, Laplacian image fusion, Partial pipelining",
author = "Liwen Gao and Hongtu Zhao and Xiujie Qu and Tianbo Wei and Peng Du",
note = "Publisher Copyright: {\textcopyright} 2018 SPIE.; 9th International Conference on Graphic and Image Processing, ICGIP 2017 ; Conference date: 14-10-2017 Through 16-10-2017",
year = "2018",
doi = "10.1117/12.2303486",
language = "English",
series = "Proceedings of SPIE - The International Society for Optical Engineering",
publisher = "SPIE",
editor = "Hui Yu and Junyu Dong",
booktitle = "Ninth International Conference on Graphic and Image Processing, ICGIP 2017",
address = "United States",
}