An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating

High-speed (~10GS/s) medium-resolution (8b) ADCs are key blocks for wideband applications. Time-domain ADCs can achieve 5GS/s single-channel speed [1], [2], but their reliance on matched gate delays leads to high sensitivity to PVT variations and device mismatches. By comparison, voltage-domain (flash/SAR/pipeline) ADCs are more robust against PVT and mismatches. However, flash ADCs are limited to 6b for their exponentially growing complexity with resolution [3]. SAR ADCs are efficient at 8b, but their limited single-channel speed (<1.5GS/s) necessitates a large number of time-interleaved (TI) channels [4], causing large implementation and calibration overhead. Pipelined ADCs are faster than SAR, but their speed is still limited to 3GS/s due to 3 basic operations in series (sampling, quantization, and amplification), as shown in Fig. 24.7.1. To speed up a pipelined stage, the quantization and amplification operations are parallelized by the post-amplification residue generation technique [5]. Nonetheless, a high-speed residue amplifier (RA) is still required to achieve the inter-stage gain, resulting in a restricted power efficiency and a limited speed enhancement to only 3.3GS/s. Furthermore, this scheme greatly increases the RA output swing, causing linearity degradation and even saturation. To address these issues, this work proposes a novel high-speed pipelined stage that parallelizes residue transfer and quantization. It eliminates the need for any voltage amplifier. By contrast, it uses differential sampling and a simple source follower (SF) to realize the inter-stage gain. The SF is linear, wideband, and low-power. Moreover, its output swing is kept the same as a conventional pipelined stage. The proposed technique enables the fastest 8b single-channel pipelined ADC running at 5GS/s. In addition, by exploiting the common-mode (CM) signal path, this work also presents a new automatic CM-regulated power-gating technique without extra switching power to further enhance the energy efficiency. Equipped with the proposed techniques, a prototype 8b 10GS/s 2-channel TI ADC realizes a FoMW of 22fJ/conv-step, which outperforms comparable ADCs with fs > 6GS/s.