Adaptive human detection approach using FPGA-based parallel architecture in reconfigurable hardware

Currently, the rapid increment of human detections has been changing people's daily life, However, the implementation is still facing the challenges caused by the restrictions of power and hardware. The computation process results in a heavy workload even though prior researches had made efforts to reduce the complexity. We focus on this issue and propose a new approach that employs the binarization-based optimization algorithm to simplify the computation processes. Our approach is designed to minimize the necessary calculations and memory space. Moreover, we have developed the field-programmable gate array-based parallel architecture to apply partial dynamic reconfiguration, which enables the remote configurations for the number of processing units. An experimental evaluation is completed in order to examine our proposed approach. According to our experimental results, the detection precision can reach a miss rate less than 1.97% and a false positive rate of 1%. The energy cost is also reduced up to 36% comparing with the prior methods.