TY - GEN
T1 - A tri-level parallel architecture for NAND flash storage system
AU - Qin, Guojie
AU - Xie, Min
AU - Liu, Guoman
AU - Jiao, Long
AU - Zhou, Boxiang
PY - 2012
Y1 - 2012
N2 - Because of its lightweight, high density, and energy-efficient characteristics, NAND flash memory has been widely used as a storage medium for electronic devices in multiple areas, such as industrial electronics, biomedical image recorder and computers. However, due to its low IO performance and long operation latency, multiple techniques are applied to the NAND storage systems to overcome these drawbacks. In this paper, we present a tri-level parallel architecture to improve the bandwidth of the storage system by hiding the operation latency through controller level, chip level and die level interleaving. The evaluation results implemented on a prototype board show that the read and write throughput of the system based on the proposed architecture could be improved enormously by utilizing multiple level interleaving techniques, and the redundancy of the flash bus could be eliminated maximally.
AB - Because of its lightweight, high density, and energy-efficient characteristics, NAND flash memory has been widely used as a storage medium for electronic devices in multiple areas, such as industrial electronics, biomedical image recorder and computers. However, due to its low IO performance and long operation latency, multiple techniques are applied to the NAND storage systems to overcome these drawbacks. In this paper, we present a tri-level parallel architecture to improve the bandwidth of the storage system by hiding the operation latency through controller level, chip level and die level interleaving. The evaluation results implemented on a prototype board show that the read and write throughput of the system based on the proposed architecture could be improved enormously by utilizing multiple level interleaving techniques, and the redundancy of the flash bus could be eliminated maximally.
KW - NAND flash memory
KW - biomedical image recorder
KW - cluster-mapping scheme
KW - tri-level parallel architecture
UR - https://www.scopus.com/pages/publications/84886432912
U2 - 10.1109/BMEI.2012.6512984
DO - 10.1109/BMEI.2012.6512984
M3 - Conference contribution
AN - SCOPUS:84886432912
SN - 9781467311816
T3 - 2012 5th International Conference on Biomedical Engineering and Informatics, BMEI 2012
SP - 1336
EP - 1340
BT - 2012 5th International Conference on Biomedical Engineering and Informatics, BMEI 2012
PB - IEEE Computer Society
T2 - 5th International Conference on Biomedical Engineering and Informatics, BMEI 2012
Y2 - 16 October 2012 through 18 October 2012
ER -