A study on effects of vacuum annealing on silicon-supported (Sn, Al)-doped Ga₂O₃ FETs as fabricated by co-sputtering

(Sn, Al)-doped Ga₂O₃ field-effect transistors (FETs) were prepared via co-sputtering technique, which offers the advantages of high compatibility with silicon technology, wafer-scale fabrication, rapid production and low cost. The electrical conductance of the as-deposited pure Ga₂O₃ film can be enhanced by Sn dopants and the wide bandgap property can be maintained through introducing Al dopants to suppress off-state current. Moreover, post-deposition annealing at various temperatures up to 800 °C in vacuum were employed to improve the device performances. Importantly, the surface of the (Sn, Al)-doped Ga₂O₃ films became progressively smoother as the annealing temperature increased toward 800 °C, achieving a low root-mean-square roughness of 0.27 nm. Meanwhile, the oxygen-related defects were greatly reduced by post-annealing for an improvement in the oxidation state of the films. In particular, the content of fully-oxidized dopants Sn⁴⁺ was dramatically improved, indicating effective activation of the Sn dopants. Consequently, exceptional electrical characteristics were obtained in the FET with an 800 °C-annealed (Sn, Al)-doped Ga₂O₃ channel, demonstrating a high on-state current of 3.9 mA/mm and an on/off ratio exceeding 10⁷. Additionally, this device also exhibited a robust high-voltage endurance as evidenced by stable operations under a continuous 100 V bias stress for 1 h and a breakdown voltage of 464 V, which is attributed to the improved film quality with a widened bandgap to 4.9 eV. This work is believed to introduce a silicon-compatible, cost-effective fabrication approach for Ga₂O₃ devices, enabling wafer-level processing and heterogeneous integration, thereby providing a scalable solution for next-generation power nanoelectronics.