@inproceedings{6cc468f54d4d465ebbf1be71efa013f1,
title = "A Simulation Comparison of Channel-All-Around and Gate-All-Around 3D Vertical Structure FeFET with IGZO Channel",
abstract = "We have compared the memory performance of vertical structure InGaZnO (IGZO) channel ferroelectric field effect transistors (FETs) with channel-all-around and gate-all-around structures by 3D TCAD simulation for high-density application. The memory window (MW), on current (Ion), and subthreshold swing (SS) are systematically studied and discussed in terms of ferroelectric film thickness, channel thickness, and diameter. It reveals that the channel-all-around structure has a larger MW and higher Ion due to the overlap region between the gate and drain/source based on this simulation, while the memory performance of the gate-all-around structure can be improved through shrinking the length of the underlap region.",
keywords = "channel-all-around, ferroelectric field effect transistor (FeFET), gate-all-around, In-Ga-Zn-O (IGZO) channel, TCAD simulation, vertical structure",
author = "Xuebin Wang and Zhijian Guo and Yutao Li and Chengji Jin and Jixuan Wu and Guanhua Yang and Yuanxiao Ma and Masaharu Kobayashi and Fei Mo and Yeliang Wang",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 17th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024 ; Conference date: 22-10-2024 Through 25-10-2024",
year = "2024",
doi = "10.1109/ICSICT62049.2024.10830976",
language = "English",
series = "2024 IEEE 17th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Fan Ye and Xiaona Zhu and Tang, \{Ting Ao\}",
booktitle = "2024 IEEE 17th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024",
address = "United States",
}