TY - JOUR
T1 - A Reconfigurable Multiresonant Switched-Capacitor Converter for 48 V Data Center Application
AU - Fu, Yu
AU - Zhao, Yucheng
AU - Qi, Jingjing
AU - Xie, Wenhao
AU - Li, Shouxiang
AU - Sun, Kai
AU - Smedley, Keyue Ma
N1 - Publisher Copyright:
© 1986-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - In the emerging two-stage architecture of 48 V data center power systems, the wide voltage range of backup batteries (36–60 V) leads to significant fluctuations in intermediate bus voltages when transmitted through fixed-gain intermediate bus converters (IBCs). To address this, a reconfigurable IBC based on multiresonant switched capacitors (SCs) is proposed in this article, achieving both 8:1 and 6:1 conversion ratios to suppress intermediate bus voltage fluctuations. The proposed topology combines a 2:1 SC with two 4:1 Fibonacci SCs, eliminating decoupling capacitors while reducing two switches. Two modulation modes with zero-current switching are described, and their corresponding component stresses are analyzed. Utilizing a two-phase output structure, the converter demonstrates low output impedance, which is estimated, decomposed, and discussed. Phase expansion can further reduce output impedance or enable dual-port outputs for dual intermediate buses. An experimental prototype with a 36–60 V input and 5.625–7.5 V output was implemented, achieving a nominal power density of 2266 W/in3 and a peak efficiency of 98.8% in 8:1 mode (3021 W/in3 and 99.1% in 6:1 mode). The reconfiguration capabilities of the proposed converter are also demonstrated.
AB - In the emerging two-stage architecture of 48 V data center power systems, the wide voltage range of backup batteries (36–60 V) leads to significant fluctuations in intermediate bus voltages when transmitted through fixed-gain intermediate bus converters (IBCs). To address this, a reconfigurable IBC based on multiresonant switched capacitors (SCs) is proposed in this article, achieving both 8:1 and 6:1 conversion ratios to suppress intermediate bus voltage fluctuations. The proposed topology combines a 2:1 SC with two 4:1 Fibonacci SCs, eliminating decoupling capacitors while reducing two switches. Two modulation modes with zero-current switching are described, and their corresponding component stresses are analyzed. Utilizing a two-phase output structure, the converter demonstrates low output impedance, which is estimated, decomposed, and discussed. Phase expansion can further reduce output impedance or enable dual-port outputs for dual intermediate buses. An experimental prototype with a 36–60 V input and 5.625–7.5 V output was implemented, achieving a nominal power density of 2266 W/in3 and a peak efficiency of 98.8% in 8:1 mode (3021 W/in3 and 99.1% in 6:1 mode). The reconfiguration capabilities of the proposed converter are also demonstrated.
KW - Data center
KW - intermediate bus converter (IBC)
KW - switched capacitor (SC)
KW - zero-current switching (ZCS)
UR - https://www.scopus.com/pages/publications/105012480329
U2 - 10.1109/TPEL.2025.3594690
DO - 10.1109/TPEL.2025.3594690
M3 - Article
AN - SCOPUS:105012480329
SN - 0885-8993
VL - 40
SP - 17958
EP - 17971
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 12
ER -