TY - GEN
T1 - A Parallel Mechanism for Fast Digital SIC in Full-Duplex ISAC systems
AU - Yang, Jie
AU - Du, Changhao
AU - Zhu, Yingshen
AU - Ruan, Hang
AU - Zhang, Zhongshan
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - A novel parallel mechanism for rapid digital-domain self-interference cancellation (SIC) in full-duplex (FD) integrated sensing and communication (ISAC) systems is proposed. The processing delay is minimized by employing a parallel cancellation architecture and substituting filtered sampling symbols with known modulation symbols, thus enabling effective and timely SIC for radar sensing. The proposed parallel SIC technique is presented through comprehensive system modeling, algorithm definition, feasibility assessment, numerical simulations, and experimental validations. The analysis shows that the proposed algorithm, with its high convergence speed, can effectively eliminate self-interference under severe conditions of self-interference and high-frequency variations, thereby enhancing the SIC capabilities of the full-duplex ISAC platform and contributing to the improvement of sensing performance.
AB - A novel parallel mechanism for rapid digital-domain self-interference cancellation (SIC) in full-duplex (FD) integrated sensing and communication (ISAC) systems is proposed. The processing delay is minimized by employing a parallel cancellation architecture and substituting filtered sampling symbols with known modulation symbols, thus enabling effective and timely SIC for radar sensing. The proposed parallel SIC technique is presented through comprehensive system modeling, algorithm definition, feasibility assessment, numerical simulations, and experimental validations. The analysis shows that the proposed algorithm, with its high convergence speed, can effectively eliminate self-interference under severe conditions of self-interference and high-frequency variations, thereby enhancing the SIC capabilities of the full-duplex ISAC platform and contributing to the improvement of sensing performance.
KW - dull-duplex (FD)
KW - Fast Convergence Algorithm
KW - Integrated Sensing and Communication (ISAC)
KW - Self-interference Cancellation (SIC)
UR - https://www.scopus.com/pages/publications/86000013952
U2 - 10.1109/ICSIDP62679.2024.10868144
DO - 10.1109/ICSIDP62679.2024.10868144
M3 - Conference contribution
AN - SCOPUS:86000013952
T3 - IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2024
BT - IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2024
Y2 - 22 November 2024 through 24 November 2024
ER -