TY - GEN
T1 - A Monolithic 3D Integration of RRAM Array with Oxide Semiconductor FET for In-memory Computing in Quantized Neural Network AI Applications
AU - Wu, Jixuan
AU - Mo, Fei
AU - Saraya, Takuya
AU - Hiramoto, Toshiro
AU - Kobayashi, Masaharu
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/6
Y1 - 2020/6
N2 - We have monolithically integrated RRAM array with oxide semiconductor channel access transistor in 3D stack, achieved uniform memory characteristics of 1 T1R cells at each layer, and demonstrated basic functionality of XNOR operation as in-memory computing for binary neural network AI applications, for the first time. The impact of RRAM bit error rate on neural network is also investigated. 3D neural network built by this architecture has high potential to enable area-efficient, low-power and low-latency computing.
AB - We have monolithically integrated RRAM array with oxide semiconductor channel access transistor in 3D stack, achieved uniform memory characteristics of 1 T1R cells at each layer, and demonstrated basic functionality of XNOR operation as in-memory computing for binary neural network AI applications, for the first time. The impact of RRAM bit error rate on neural network is also investigated. 3D neural network built by this architecture has high potential to enable area-efficient, low-power and low-latency computing.
UR - https://www.scopus.com/pages/publications/85098189319
U2 - 10.1109/VLSITechnology18217.2020.9265062
DO - 10.1109/VLSITechnology18217.2020.9265062
M3 - Conference contribution
AN - SCOPUS:85098189319
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020
Y2 - 16 June 2020 through 19 June 2020
ER -