A miniaturized universal architecture for radar signal processing systems

This paper proposes and examines a type of miniaturized universal system architecture for radar signal processing platforms. This architecture can satisfy the urgent demands both on high-performance computing, parallelizable processing, scalability, ability to reconfigure in today's universal radar signal processing systems, and on strict limitations for volume, weight, power consumption, and physical shapes in airborne or missile-borne Synthetic Aperture Radar (SAR) real time imaging processing systems. Based on the new architecture, numerous characteristics of the system hardware architecture were anatomized. The performance and structure of the key processing elements, such as hybrid parallel processing nodes, high-speed serial switching networks and distributed storing was discussed in detail. A detailed analysis of how to implement system parallelization and extension with different topologies was performed. Finally, a successful application case in an airborne SAR processing system was presented.