@inproceedings{15d38320ed444611b5106d215bce7e62,
title = "A Low-Power Low-Cost CML-Based Divider-by-2 with Quadrature Outputs",
abstract = "An RF divider-by-2 with quadrature outputs was designed in 65-nm CMOS technology. The divider consists of two cascaded current-mode logic (CML) latches that are cross- coupled, achieving a frequency range of 2 \textasciitilde{} 9.5 GHz with the sensitivity from -38.9 dBm to 0 dBm. The proposed divider consumes 0.47 mW from a 1.2-V supply and has a core area of 528 μm2. The phase noise of -138.9 dBc/Hz at 1-MHz offset frequency is also accomplished. With tri-state inverter based cross-couple structure, the presented circuit contributes to a low- power low-cost design of RF quadrature signal generators with the phase error less than 1.6°.",
keywords = "CML, RF Frequency divider, low cost, low power, quadrature output",
author = "Chen Wang and Ziru Zhang and Yuyang Ding and Bo Zhou",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 7th International Conference on Electronics and Electrical Engineering Technology, EEET 2024 ; Conference date: 06-12-2024 Through 08-12-2024",
year = "2024",
doi = "10.1109/EEET64351.2024.00012",
language = "English",
series = "Proceedings - 2024 7th International Conference on Electronics and Electrical Engineering Technology, EEET 2024",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "7--10",
booktitle = "Proceedings - 2024 7th International Conference on Electronics and Electrical Engineering Technology, EEET 2024",
address = "United States",
}