A high performance FFT processor based on conflict-free memory access

A new design method of FFT processor is proposed based on conflict-free memory access to satisfy the requirements for both high data throughout rate and low logic resource utilization. Aiming to realize a 1024/256 point compatible FFT processor with radix-4, decimation in time algorithm and block floating point arithmetic, four separate memory blocks are used to achieve conflict-free parallel data input and output for butterfly computation unit. Compared with some existing FFT processors, the design and verification results indicate that the proposed FFT processor has better real-time performance, low structure complexity and logic resource occupation.