TY - GEN
T1 - A Heterogeneous FPGA-based Accelerator Design for Efficient and Low-cost Point Clouds Deep Learning Inference
AU - Xu, Jinling
AU - Wang, Yonggui
AU - Zhouy, Wenbiao
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The neural networks on 3D data and applications have emerged in the past five years. However, there are only a few dedicated hardware designs were proposed for 3D data and algorithms. Meanwhile, they lack flexibility and adaptation for the fast evolvement of software algorithms. We propose a heterogeneous accelerator design on Xilinx Zynq and Zynq UltraScale+ platform. An innovative vector pipeline is designed in the accelerator that can reach the near limitation of BRAM frequency, and it gives the final design frequency closure at 550MHz with 100% DSP usage.
AB - The neural networks on 3D data and applications have emerged in the past five years. However, there are only a few dedicated hardware designs were proposed for 3D data and algorithms. Meanwhile, they lack flexibility and adaptation for the fast evolvement of software algorithms. We propose a heterogeneous accelerator design on Xilinx Zynq and Zynq UltraScale+ platform. An innovative vector pipeline is designed in the accelerator that can reach the near limitation of BRAM frequency, and it gives the final design frequency closure at 550MHz with 100% DSP usage.
UR - https://www.scopus.com/pages/publications/85142495218
U2 - 10.1109/ISCAS48785.2022.9937592
DO - 10.1109/ISCAS48785.2022.9937592
M3 - Conference contribution
AN - SCOPUS:85142495218
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2725
EP - 2729
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Y2 - 27 May 2022 through 1 June 2022
ER -