TY - GEN
T1 - A CMOS Hybrid Common-Gate Current-Integrating Sampler with >37dB SNDR Across 51GHz BW in a 128GS/s Front-End
AU - Dai, Jun
AU - Zhong, Yi
AU - Tao, Yunsong
AU - Zhang, Aodong
AU - Zhan, Mingtao
AU - Zhang, Hao
AU - Jie, Lu
AU - Sun, Nan
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - This work proposes a CMOS hybrid common-gate current integrating sampler to address linearity, BW, and jitter limitations in prior wideband ADC front-ends. The front-end employs a hybrid common-gate V-I converter, transformer-coupled inductive peaking, and an automatic power-gating hold buffer, enabling 48.1dB SFDR and 38.6dB SNDR near its 52GHz BW-3dB. This work demonstrates superior SNDRBW (measured near BW3dB), outperforming prior samplers/ADCs reported in ISSCC/JSSC/VLSI with BW>30GHz.
AB - This work proposes a CMOS hybrid common-gate current integrating sampler to address linearity, BW, and jitter limitations in prior wideband ADC front-ends. The front-end employs a hybrid common-gate V-I converter, transformer-coupled inductive peaking, and an automatic power-gating hold buffer, enabling 48.1dB SFDR and 38.6dB SNDR near its 52GHz BW-3dB. This work demonstrates superior SNDRBW (measured near BW3dB), outperforming prior samplers/ADCs reported in ISSCC/JSSC/VLSI with BW>30GHz.
UR - https://www.scopus.com/pages/publications/105035351717
U2 - 10.1109/ISSCC49663.2026.11409117
DO - 10.1109/ISSCC49663.2026.11409117
M3 - Conference contribution
AN - SCOPUS:105035351717
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 378
EP - 380
BT - 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026
Y2 - 15 February 2026 through 19 February 2026
ER -