A 75-MHz-BW 3rd-order Time-Interleaved Noise-Shaping SAR ADC with Shared EF-CIFF Loop Filter and Ring Buffer

This paper presents a two-channel time-interleaved (TI) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with wide bandwidth, high resolution, and low power consumption. A shared loop filter realizes residue filtering between interleaved channels by midway feedback. The error feedback-cascaded integrator feedforward (EF-CIFF) loop filter architecture is adopted to achieve 3rd-order noise shaping with only one residue amplifier. A ring buffer is adopted to provide accurate gain by forming an inner feedback loop. PVT robust biasing and split current source architecture make the ring buffer immune to PVT variation and V_CM mismatch. A prototype ADC in 28nm CMOS achieves 62.0 dB SNDR over 75 MHz bandwidth and consumes 5.9 mW, leading to a FoMs of 163 dB.