A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application

Chengying Chen; Liming Chen; Xinghua Wang; Feng Zhang

doi:10.1109/ISCAS.2018.8351783

A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application

Chengying Chen
, Liming Chen
, Xinghua Wang
, Feng Zhang

集成电路与电子学院

Xiamen University of Technology
Chinese Academy of Sciences

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

7 引用（Scopus）

摘要

For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2^nd Sigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.

源语言	英语
主期刊名	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
出版商	Institute of Electrical and Electronics Engineers Inc.
ISBN（电子版）	9781538648810
DOI	https://doi.org/10.1109/ISCAS.2018.8351783
出版状态	已出版 - 26 4月 2018
活动	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, 意大利期限: 27 5月 2018 → 30 5月 2018

丛书

姓名	Proceedings - IEEE International Symposium on Circuits and Systems
卷	2018-May
ISSN（印刷版）	0271-4310

会议

会议	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
国家/地区	意大利
市	Florence
时期	27/05/18 → 30/05/18

访问文件

10.1109/ISCAS.2018.8351783

其它文件与链接

链接到 Scopus 的出版物

引用此

Chen, C., Chen, L., Wang, X., & Zhang, F. (2018). A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. 在 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings 期刊论文 8351783 (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351783

@inproceedings{8a35bf05dcba4860a929ebc9b0057a00,

title = "A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application",

abstract = "For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2nd Sigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.",

keywords = "analog front-end, electrocardiogram, electroencephalogram, low noise, low power",

author = "Chengying Chen and Liming Chen and Xinghua Wang and Feng Zhang",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

year = "2018",

month = apr,

day = "26",

doi = "10.1109/ISCAS.2018.8351783",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Chen, C, Chen, L, Wang, X & Zhang, F 2018, A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. 在 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351783, Proceedings - IEEE International Symposium on Circuits and Systems, 卷 2018-May, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, 意大利, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8351783

A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. / Chen, Chengying; Chen, Liming; Wang, Xinghua 等.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8351783 (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 2018-May).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application

AU - Chen, Chengying

AU - Chen, Liming

AU - Wang, Xinghua

AU - Zhang, Feng

PY - 2018/4/26

Y1 - 2018/4/26

N2 - For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2nd Sigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.

AB - For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2nd Sigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.

KW - analog front-end

KW - electrocardiogram

KW - electroencephalogram

KW - low noise

KW - low power

UR - https://www.scopus.com/pages/publications/85057089000

U2 - 10.1109/ISCAS.2018.8351783

DO - 10.1109/ISCAS.2018.8351783

M3 - Conference contribution

AN - SCOPUS:85057089000

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018

Y2 - 27 May 2018 through 30 May 2018

ER -

A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application

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