A 12-b 3-GS/s Pipelined ADC With Piecewise-Linear Gain Nonlinearity Calibration

This article presents a novel piecewise-linear gain nonlinearity calibration technique with low computational complexity and background coefficient extraction, enabling the use of open-loop amplifiers in pipelined ADCs for high energy efficiency. In addition to the gain nonlinearity calibration, circuit innovations such as a dual-path amplification scheme and a high-speed flash comparator are also introduced. Incorporating these techniques, a prototype 12-b 3-GS/s pipelined ADC is fabricated in a 28-nm CMOS process. Including the on-chip calibration engine, it consumes 50.5 mW and achieves an SNDR of 58.8 dB with a 1.5-GHz input, corresponding to a competitive FoMS of 164 dB.