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A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer

  • Jianhua Lu*
  • , Zhigong Wang
  • , Lei Tian
  • , Rui Tao
  • , Haitao Chen
  • , Tingting Xie
  • , Zhiheng Chen
  • , Jun Feng
  • , Yi Dong
  • , Shizhong Xie
  • *此作品的通讯作者
  • Southeast University, Nanjing
  • Tsinghua University

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

A 4.8 Gbit/s 4:1 multiplexer was designed in source coupled logic and fabricated in 0.35 μm CMOS technology. It has a power dissipation of less than 1W from a 5V supply and a size of 1×1.05 mm2, and can be directly applied to an optical fiber link at STM-16 (2.488 Gbit/s) level of synchronous digital hierarchy (SDH).

源语言英语
主期刊名2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings
编辑Lemin Li
出版商Institute of Electrical and Electronics Engineers Inc.
824-826
页数3
ISBN(电子版)0780375475, 9780780375475
DOI
出版状态已出版 - 2002
已对外发布
活动1st International Conference on Communications, Circuits and Systems, ICCCAS 2002 - Chengdu, 中国
期限: 29 6月 20021 7月 2002

丛书

姓名2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings

会议

会议1st International Conference on Communications, Circuits and Systems, ICCCAS 2002
国家/地区中国
Chengdu
时期29/06/021/07/02

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