TY - GEN
T1 - 3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM
AU - Zhang, Min
AU - Zhang, Youtao
AU - Li, Xiaopeng
AU - Liu, Ao
AU - Qian, Feng
PY - 2009
Y1 - 2009
N2 - This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.
AB - This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.
KW - Analog-to-digital converter
KW - Digital radio frequency memory
KW - Digital-to-analog converter
KW - Phase digitizing
UR - https://www.scopus.com/pages/publications/77949342967
U2 - 10.1109/ASICON.2009.5351485
DO - 10.1109/ASICON.2009.5351485
M3 - Conference contribution
AN - SCOPUS:77949342967
SN - 9781424438686
T3 - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
SP - 226
EP - 229
BT - ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009
Y2 - 20 October 2009 through 23 October 2009
ER -