10-Gb/s 1:4 demultiplexer in 0.25 μm CMOS

Lei Tian; Zhigong Wang; Haitao Chen; Tingting Xie; Jianhua Lu; Rui Tao; Yi Dong; Shizhong Xie

doi:10.1117/12.444544

10-Gb/s 1:4 demultiplexer in 0.25 μm CMOS

Lei Tian
, Zhigong Wang
, Haitao Chen
, Tingting Xie
, Jianhua Lu
, Rui Tao
, Yi Dong
, Shizhong Xie

Southeast University, Nanjing
Tsinghua University

科研成果: 期刊稿件 › 文章 › 同行评审

2 引用（Scopus）

摘要

This paper describes a 1:4 demultiplexer in a standard 0.25 μm CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1 mm² area. It consumes 693 mW from a 3.3 V supply. The operating bit rates is higher than 10 Gb/s.

源语言	英语
页（从-至）	121-124
页数	4
期刊	Proceedings of SPIE - The International Society for Optical Engineering
卷	4603
DOI	https://doi.org/10.1117/12.444544
出版状态	已出版 - 2001
已对外发布	是

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abstract = "This paper describes a 1:4 demultiplexer in a standard 0.25 μm CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1 mm2 area. It consumes 693 mW from a 3.3 V supply. The operating bit rates is higher than 10 Gb/s.",

keywords = "0.25 μm CMOS, 1:4 Demultiplexer, High-speed ICs, SCL, SDH system",

author = "Lei Tian and Zhigong Wang and Haitao Chen and Tingting Xie and Jianhua Lu and Rui Tao and Yi Dong and Shizhong Xie",

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AU - Tian, Lei

AU - Wang, Zhigong

AU - Chen, Haitao

AU - Xie, Tingting

AU - Lu, Jianhua

AU - Tao, Rui

AU - Dong, Yi

AU - Xie, Shizhong

PY - 2001

Y1 - 2001

N2 - This paper describes a 1:4 demultiplexer in a standard 0.25 μm CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1 mm2 area. It consumes 693 mW from a 3.3 V supply. The operating bit rates is higher than 10 Gb/s.

AB - This paper describes a 1:4 demultiplexer in a standard 0.25 μm CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1 mm2 area. It consumes 693 mW from a 3.3 V supply. The operating bit rates is higher than 10 Gb/s.

KW - 0.25 μm CMOS

KW - 1:4 Demultiplexer

KW - High-speed ICs

KW - SCL

KW - SDH system

UR - https://www.scopus.com/pages/publications/0035771281

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JF - Proceedings of SPIE - The International Society for Optical Engineering

ER -

10-Gb/s 1:4 demultiplexer in 0.25 μm CMOS

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