高速低复杂度并行盲均衡的研究与FPGA实现

Engineering

• Blind Equalization 100%
• Clock Frequency 33%
• Demodulation 66%
• Field Programmable Gate Arrays 100%
• Hardware Cost 33%
• Intersymbol Interference 33%
• Model Constant 33%
• Multipath 33%
• Sampling Time 33%
• Symbol Rate 66%

Computer Science

• Arithmetic Model 33%
• Blind Equalization 100%
• Clock Frequency 33%
• Hardware Cost 33%
• Hardware Platform 33%
• Multipath 33%
• Parallel Structure 33%
• Throughput Data 33%