应用于K波段分数分频频率综合器的多模分频器设计与优化

Zheng Chen Wang; Zhao Bo Wu; Quan Wen Qi; Xing Hua Wang

doi:10.15918/j.tbit1001-0645.2017.329

应用于K波段分数分频频率综合器的多模分频器设计与优化

Zheng Chen Wang
, Zhao Bo Wu
, Quan Wen Qi
, Xing Hua Wang^*

^*此作品的通讯作者

集成电路与电子学院

Beijing Institute of Technology

科研成果: 期刊稿件 › 文章 › 同行评审

1 引用（Scopus）

摘要

A multi-modulus-divider (MMD) was designed based on TSMC 90 nm CMOS process, achieving a division range of the MMD from 32 to 39. The block diagram of MMD, including double-modulus-divider, S counter and P counter were discussed in detail. Time sequence requirement of the P counters with and without retime circuit were analyzed and discussed. The proposed MMD was integrated into a K-band fractional-N frequency synthesizer. The measurement results show that in-band phase noise performance can be optimized about 15 dB through the modified MMD. The measurement results exhibit the phase noise performance can achieve -81.3 dBc/Hz and -72.44 dBc/Hz at 10 kHz frequency offset and 1 kHz frequency offset, respectively.

投稿的翻译标题	Design and Optimization of Multi-Modulus-Divider for K-Band Fractional-N Frequency Synthesizer
源语言	繁体中文
页（从-至）	1187-1191
页数	5
期刊	Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
卷	39
期	11
DOI	https://doi.org/10.15918/j.tbit1001-0645.2017.329
出版状态	已出版 - 1 11月 2019

关键词

Fractional-N frequency synthesizer
Multi-modulus-divider
Retime circuit technique

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10.15918/j.tbit1001-0645.2017.329

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链接到 Scopus 的出版物

引用此

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abstract = "A multi-modulus-divider (MMD) was designed based on TSMC 90 nm CMOS process, achieving a division range of the MMD from 32 to 39. The block diagram of MMD, including double-modulus-divider, S counter and P counter were discussed in detail. Time sequence requirement of the P counters with and without retime circuit were analyzed and discussed. The proposed MMD was integrated into a K-band fractional-N frequency synthesizer. The measurement results show that in-band phase noise performance can be optimized about 15 dB through the modified MMD. The measurement results exhibit the phase noise performance can achieve -81.3 dBc/Hz and -72.44 dBc/Hz at 10 kHz frequency offset and 1 kHz frequency offset, respectively.",

keywords = "Fractional-N frequency synthesizer, Multi-modulus-divider, Retime circuit technique",

author = "Wang, \{Zheng Chen\} and Wu, \{Zhao Bo\} and Qi, \{Quan Wen\} and Wang, \{Xing Hua\}",

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doi = "10.15918/j.tbit1001-0645.2017.329",

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AU - Wang, Zheng Chen

AU - Wu, Zhao Bo

AU - Qi, Quan Wen

AU - Wang, Xing Hua

PY - 2019/11/1

Y1 - 2019/11/1

N2 - A multi-modulus-divider (MMD) was designed based on TSMC 90 nm CMOS process, achieving a division range of the MMD from 32 to 39. The block diagram of MMD, including double-modulus-divider, S counter and P counter were discussed in detail. Time sequence requirement of the P counters with and without retime circuit were analyzed and discussed. The proposed MMD was integrated into a K-band fractional-N frequency synthesizer. The measurement results show that in-band phase noise performance can be optimized about 15 dB through the modified MMD. The measurement results exhibit the phase noise performance can achieve -81.3 dBc/Hz and -72.44 dBc/Hz at 10 kHz frequency offset and 1 kHz frequency offset, respectively.

AB - A multi-modulus-divider (MMD) was designed based on TSMC 90 nm CMOS process, achieving a division range of the MMD from 32 to 39. The block diagram of MMD, including double-modulus-divider, S counter and P counter were discussed in detail. Time sequence requirement of the P counters with and without retime circuit were analyzed and discussed. The proposed MMD was integrated into a K-band fractional-N frequency synthesizer. The measurement results show that in-band phase noise performance can be optimized about 15 dB through the modified MMD. The measurement results exhibit the phase noise performance can achieve -81.3 dBc/Hz and -72.44 dBc/Hz at 10 kHz frequency offset and 1 kHz frequency offset, respectively.

KW - Fractional-N frequency synthesizer

KW - Multi-modulus-divider

KW - Retime circuit technique

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DO - 10.15918/j.tbit1001-0645.2017.329

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JO - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

JF - Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology

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ER -

应用于K波段分数分频频率综合器的多模分频器设计与优化

摘要

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