基于LVDS的高速数据回读系统设计

The pulse width of the measured parameter signal of a certain type of projectile body is very narrow in the process of launching and flying, the off-line acquisition system used high sampling rate analog to digital converter (ADC) at design time, there were problems that solid-state memory (Flash) finally stored too much data, the existing readback system speed was too slow, the readback time was too long, and the range experiment cound not continue. Based on the above issues, a high-speed read-back system was designed. The system used field programmable gate array (FPGA) as the main control module, and used the internal resources of FPGA to build a low-voltage differential signal (LVDS) interface for data readback. Used visual studio to compile the host computer, complete the interaction of instructions and data, and realize the timely readback of data. Experimented verifies that the readback rate can reach 100 MB/s without error or frame loss.