基于FPGA的二维双向CFAR处理器的设计与实现

In radar adaptive detection, one-dimensional CFAR processor can only perform target detection in a single dimension.Based on the one-dimensional CFAR algorithm, a new method was proposed to implement a two-dimensional bidirectional CFAR processor structure on FPGA.Considering the detection information of the distance dimension and the Doppler dimension synchronously, the structure was arranged to improve the detection accuracy.The processor was designed for six algorithm options, supporting CA, GO, SO, OSCA, OSGO, and OSSO CFAR detectors, and also supporting configurable number of reference cells, number of protection cells, ranking values, and threshold factors to be applied in a variety of clutter environments.Experimental results show that, when the signal-to-noise ratio is 12 dB, the detection probability of the six detectors can reach above 80%.The maximum integrated clock frequency of this processor is 137 MHz, and the logic unit used is much smaller than the FPGA resources, which can meet the requirements of practical engineering applications.