Abstract
A novel silicon-insulator-silicon through-silicon-via (TSV) using ultra-low-resistivity silicon pillar as the conductor, while polymer benzocyclobutene as an insulation layer was successfully fabricated. With the help of on-wafer deembedding structure and vector network analyzer, wideband parasitic capacitance characteristics of a single TSV were accurately measured. Results show that stable capacitance over frequency (up to 50 GHz) and operation voltage (-20-20 V) is obtained with good wafer-level uniformity. Compared with the conventional Cu core TSV, the proposed structure not only exhibits a small and stable capacitance, but also involves a much simpler and cost-effective process flow.
| Original language | English |
|---|---|
| Article number | 7349106 |
| Pages (from-to) | 216-219 |
| Number of pages | 4 |
| Journal | IEEE Electron Device Letters |
| Volume | 37 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 1 Feb 2016 |
Keywords
- Capacitance
- Silicon-insulator-silicon (SIS)
- Three-dimensional integration
- Through-silicon-via (TSV)
- Wideband