Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications

Yangyang Yan; Yingtao Ding; Qianwen Chen; Kangwook Lee; Takafumi Fukushima; Mitsu Koyanagi

doi:10.1109/3DIC.2015.7334568

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications

Yangyang Yan, Yingtao Ding, Qianwen Chen, Kangwook Lee, Takafumi Fukushima, Mitsu Koyanagi

School of Integrated Circuits and Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Citations (Scopus)

Abstract

In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details about the proposed technique were illustrated and test structures of silicon blind vias with diameter of about 6μm and depth of about 51μm were successfully sidewall coated with polyimide liner with step coverage around 30% utilizing the technique proposed. For thermal reliability investigations of the cured polyimide liner, X-ray photoelectron spectroscopy (XPS) analysis was performed to get the chemical state information of the cured polyimide liner. Also, planar metal-insulator-semiconductor (MIS) capacitor which involves polyimide as insulator was built to investigate electrical properties of polyimide liner formed. Electrical characteristics such as capacitance-voltage(C-V) curve and leakage current under biased voltage up to 20V were measured. All these results showed the potential of the technique proposed to be applied to high aspect ratio TSVs for 3D integration.

Original language	English
Title of host publication	2015 International 3D Systems Integration Conference, 3DIC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	TS5.2.1-TS5.2.5
ISBN (Electronic)	9781467393850
DOIs	https://doi.org/10.1109/3DIC.2015.7334568
Publication status	Published - 20 Nov 2015
Event	International 3D Systems Integration Conference, 3DIC 2015 - Sendai, Japan Duration: 31 Aug 2015 → 2 Sept 2015

Publication series

Name	2015 International 3D Systems Integration Conference, 3DIC 2015

Conference

Conference	International 3D Systems Integration Conference, 3DIC 2015
Country/Territory	Japan
City	Sendai
Period	31/08/15 → 2/09/15

Keywords

Through-Silicon-Vias (TSVs)
polyimide liner
three-dimensional (3D) integration
vacuum-assisted spin coating

Access to Document

10.1109/3DIC.2015.7334568

Cite this

Yan, Y., Ding, Y., Chen, Q., Lee, K., Fukushima, T., & Koyanagi, M. (2015). Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. In 2015 International 3D Systems Integration Conference, 3DIC 2015 (pp. TS5.2.1-TS5.2.5). Article 7334568 (2015 International 3D Systems Integration Conference, 3DIC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/3DIC.2015.7334568

@inproceedings{da69e54ee652477c910832e281110e18,

title = "Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications",

abstract = "In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details about the proposed technique were illustrated and test structures of silicon blind vias with diameter of about 6μm and depth of about 51μm were successfully sidewall coated with polyimide liner with step coverage around 30% utilizing the technique proposed. For thermal reliability investigations of the cured polyimide liner, X-ray photoelectron spectroscopy (XPS) analysis was performed to get the chemical state information of the cured polyimide liner. Also, planar metal-insulator-semiconductor (MIS) capacitor which involves polyimide as insulator was built to investigate electrical properties of polyimide liner formed. Electrical characteristics such as capacitance-voltage(C-V) curve and leakage current under biased voltage up to 20V were measured. All these results showed the potential of the technique proposed to be applied to high aspect ratio TSVs for 3D integration.",

keywords = "Through-Silicon-Vias (TSVs), polyimide liner, three-dimensional (3D) integration, vacuum-assisted spin coating",

author = "Yangyang Yan and Yingtao Ding and Qianwen Chen and Kangwook Lee and Takafumi Fukushima and Mitsu Koyanagi",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; International 3D Systems Integration Conference, 3DIC 2015 ; Conference date: 31-08-2015 Through 02-09-2015",

year = "2015",

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doi = "10.1109/3DIC.2015.7334568",

language = "English",

series = "2015 International 3D Systems Integration Conference, 3DIC 2015",

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Yan, Y, Ding, Y, Chen, Q, Lee, K, Fukushima, T & Koyanagi, M 2015, Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. in 2015 International 3D Systems Integration Conference, 3DIC 2015., 7334568, 2015 International 3D Systems Integration Conference, 3DIC 2015, Institute of Electrical and Electronics Engineers Inc., pp. TS5.2.1-TS5.2.5, International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, 31/08/15. https://doi.org/10.1109/3DIC.2015.7334568

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. / Yan, Yangyang; Ding, Yingtao; Chen, Qianwen et al.
2015 International 3D Systems Integration Conference, 3DIC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. TS5.2.1-TS5.2.5 7334568 (2015 International 3D Systems Integration Conference, 3DIC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications

AU - Yan, Yangyang

AU - Ding, Yingtao

AU - Chen, Qianwen

AU - Lee, Kangwook

AU - Fukushima, Takafumi

AU - Koyanagi, Mitsu

PY - 2015/11/20

Y1 - 2015/11/20

N2 - In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details about the proposed technique were illustrated and test structures of silicon blind vias with diameter of about 6μm and depth of about 51μm were successfully sidewall coated with polyimide liner with step coverage around 30% utilizing the technique proposed. For thermal reliability investigations of the cured polyimide liner, X-ray photoelectron spectroscopy (XPS) analysis was performed to get the chemical state information of the cured polyimide liner. Also, planar metal-insulator-semiconductor (MIS) capacitor which involves polyimide as insulator was built to investigate electrical properties of polyimide liner formed. Electrical characteristics such as capacitance-voltage(C-V) curve and leakage current under biased voltage up to 20V were measured. All these results showed the potential of the technique proposed to be applied to high aspect ratio TSVs for 3D integration.

AB - In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details about the proposed technique were illustrated and test structures of silicon blind vias with diameter of about 6μm and depth of about 51μm were successfully sidewall coated with polyimide liner with step coverage around 30% utilizing the technique proposed. For thermal reliability investigations of the cured polyimide liner, X-ray photoelectron spectroscopy (XPS) analysis was performed to get the chemical state information of the cured polyimide liner. Also, planar metal-insulator-semiconductor (MIS) capacitor which involves polyimide as insulator was built to investigate electrical properties of polyimide liner formed. Electrical characteristics such as capacitance-voltage(C-V) curve and leakage current under biased voltage up to 20V were measured. All these results showed the potential of the technique proposed to be applied to high aspect ratio TSVs for 3D integration.

KW - Through-Silicon-Vias (TSVs)

KW - polyimide liner

KW - three-dimensional (3D) integration

KW - vacuum-assisted spin coating

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U2 - 10.1109/3DIC.2015.7334568

DO - 10.1109/3DIC.2015.7334568

M3 - Conference contribution

AN - SCOPUS:84962290661

T3 - 2015 International 3D Systems Integration Conference, 3DIC 2015

SP - TS5.2.1-TS5.2.5

BT - 2015 International 3D Systems Integration Conference, 3DIC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - International 3D Systems Integration Conference, 3DIC 2015

Y2 - 31 August 2015 through 2 September 2015

ER -

Yan Y, Ding Y, Chen Q, Lee K, Fukushima T, Koyanagi M. Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. In 2015 International 3D Systems Integration Conference, 3DIC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. TS5.2.1-TS5.2.5. 7334568. (2015 International 3D Systems Integration Conference, 3DIC 2015). doi: 10.1109/3DIC.2015.7334568

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications

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