Two-channel time-interleaved pipelined ADC using shared amplifiers

Zhuo Zhang*, Shun'an Zhong, Xing Hua Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A pipelined ADC using shared amplifiers in two-channel time-interleaved design is proposed. The two channels have a unify sample and hold amplifier. In the time-interleaved pipelined part, the large mismatch between the channels is reduced by the shared amplifier in the same stage. And power consumption and chip area also been decreased. Under SMIC 0.35um 1P6M CMOS process with 3.3V supply, the SNR is higher than 60dB with the condition that the sampling rate is 200MHz and the input frequency is scanned from 1MHz to 80MHz. The typical current consumption is about 40mA.

Original languageEnglish
Title of host publication2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Pages92-96
Number of pages5
DOIs
Publication statusPublished - 2010
Event2nd International Conference on Computer and Automation Engineering, ICCAE 2010 - Singapore, Singapore
Duration: 26 Feb 201028 Feb 2010

Publication series

Name2010 The 2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Volume3

Conference

Conference2nd International Conference on Computer and Automation Engineering, ICCAE 2010
Country/TerritorySingapore
CitySingapore
Period26/02/1028/02/10

Keywords

  • Amplifier shared
  • CMOS
  • Piepelined
  • Time-interleaved

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