Tunneling leakage current reduction in junctionless transistors using a lightly doped region near drain

  • Wenjie Chen
  • , Renrong Liang
  • , Jing Wang
  • , Jun Xu Tsinghua

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A novel double gate junctionless transistor with a lightly doped region near drain (LD-JLT) is investigated through two-dimensional numerical simulations and compared with the conventional double gate junctionless transistor (C-JLT). Simulation results show that the OFF-state current of our proposed LD-JLT is more than eight orders smaller than that of the C-JNT due to the increased tunneling barrier width and reduced band-to-band-tunneling (BTBT) generation rate. Furthermore, the channel length dependency of the LD-JLT and the C-JLT shows that our proposed LD-JLT exhibits superior scaling capability.

Original languageEnglish
Title of host publicationProceedings - 2018 7th International Symposium on Next-Generation Electronics, ISNE 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-3
Number of pages3
ISBN (Electronic)9781538614457
DOIs
Publication statusPublished - 22 Jun 2018
Externally publishedYes
Event7th International Symposium on Next-Generation Electronics, ISNE 2018 - Taipei, Taiwan, Province of China
Duration: 7 May 20189 May 2018

Publication series

NameProceedings - 2018 7th International Symposium on Next-Generation Electronics, ISNE 2018

Conference

Conference7th International Symposium on Next-Generation Electronics, ISNE 2018
Country/TerritoryTaiwan, Province of China
CityTaipei
Period7/05/189/05/18

Keywords

  • Band to band tunneling
  • Junctionless transistor
  • Leakage current

Fingerprint

Dive into the research topics of 'Tunneling leakage current reduction in junctionless transistors using a lightly doped region near drain'. Together they form a unique fingerprint.

Cite this