Time-varying network architecture of fractional multiple sampling rate converter and its FPGA implementation

The design method for the efficient time-varying network architecture of the fractional multiple sampling rate converter is presented and its field programmable gate array (FPGA) is implemented. Compared the polyphase architecture with the time-varying network architecture of the fractional multiple sampling rate converter, the time-varying architecture overcomes a fractional delay problem when implementing the fractional multiple sampling rate converter, and so its structure is simple. This design for the parallel pipeline structure is used to improve the processing speed. The operated filtering at a low sampling rate can reduce the count quantity. When the fractional multiple sampling rate is I/D= 256/1023, the whole design is implemented with one chip of XC2V250-5 FPGA, the use factor of the chip is 61% and the maximum frequency is 92.225 MHz. The design is verified by simulation and measurement results.