The implementation method about verifying to VLIW DSP

Ding Xie; He Hu; Zhang Yanjun; Sun Yihe; Yu Yongkang

The implementation method about verifying to VLIW DSP

Ding Xie^*
, He Hu
, Zhang Yanjun
, Sun Yihe
, Yu Yongkang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator μGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9%. This result shows the feasibility and effectiveness of our method.

Original language	English
Title of host publication	ASICON 2005
Subtitle of host publication	2005 6th International Conference on ASIC, Proceedings
Pages	673-676
Number of pages	4
Publication status	Published - 2005
Externally published	Yes
Event	ASICON 2005: 2005 6th International Conference on ASIC - Shanghai, China Duration: 24 Oct 2005 → 27 Oct 2005

Publication series

Name	ASICON 2005: 2005 6th International Conference on ASIC, Proceedings
Volume	2

Conference

Conference	ASICON 2005: 2005 6th International Conference on ASIC
Country/Territory	China
City	Shanghai
Period	24/10/05 → 27/10/05

Cite this

@inproceedings{1b6841a8329647edbf3327dc54bb0039,

title = "The implementation method about verifying to VLIW DSP",

abstract = "Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator μGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9\%. This result shows the feasibility and effectiveness of our method.",

author = "Ding Xie and He Hu and Zhang Yanjun and Sun Yihe and Yu Yongkang",

year = "2005",

language = "English",

isbn = "0780392108",

series = "ASICON 2005: 2005 6th International Conference on ASIC, Proceedings",

pages = "673--676",

booktitle = "ASICON 2005",

note = "ASICON 2005: 2005 6th International Conference on ASIC ; Conference date: 24-10-2005 Through 27-10-2005",

}

The implementation method about verifying to VLIW DSP. / Xie, Ding; Hu, He; Yanjun, Zhang et al.
ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. 2005. p. 673-676 1611418 (ASICON 2005: 2005 6th International Conference on ASIC, Proceedings; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - The implementation method about verifying to VLIW DSP

AU - Xie, Ding

AU - Hu, He

AU - Yanjun, Zhang

AU - Yihe, Sun

AU - Yongkang, Yu

PY - 2005

Y1 - 2005

N2 - Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator μGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9%. This result shows the feasibility and effectiveness of our method.

AB - Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator μGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9%. This result shows the feasibility and effectiveness of our method.

UR - https://www.scopus.com/pages/publications/33847275258

M3 - Conference contribution

AN - SCOPUS:33847275258

SN - 0780392108

SN - 9780780392106

T3 - ASICON 2005: 2005 6th International Conference on ASIC, Proceedings

SP - 673

EP - 676

BT - ASICON 2005

T2 - ASICON 2005: 2005 6th International Conference on ASIC

Y2 - 24 October 2005 through 27 October 2005

ER -

The implementation method about verifying to VLIW DSP

Abstract

Publication series

Conference

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