Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

Razaidi Hussin; Louis Gerrer; Jie Ding; Liping Wang; Salvatore M. Amoroso; Binjie Cheng; Dave Reid; Pieter Weckx; Marco Simicic; Jacopo Franco; Annelies Vanderheyden; Danielle Vanhaeren; Naoto Horiguchi; Ben Kaczer; Asen Asenov

doi:10.1109/ESSDERC.2015.7324758

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

Razaidi Hussin, Louis Gerrer, Jie Ding, Liping Wang, Salvatore M. Amoroso, Binjie Cheng, Dave Reid, Pieter Weckx, Marco Simicic, Jacopo Franco, Annelies Vanderheyden, Danielle Vanhaeren, Naoto Horiguchi, Ben Kaczer, Asen Asenov

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time.

Original language	English
Title of host publication	ESSDERC 2015 - Proceedings of the 45th European Solid-State Device Research Conference
Editors	Tibor Grasser, Wolfgang Pribyl, Martin Schrems
Publisher	Editions Frontieres
Pages	238-241
Number of pages	4
ISBN (Electronic)	9781467371339
DOIs	https://doi.org/10.1109/ESSDERC.2015.7324758
Publication status	Published - 10 Nov 2015
Externally published	Yes
Event	45th European Solid-State Device Research Conference, ESSDERC 2015 - Graz, Austria Duration: 14 Sept 2015 → 18 Sept 2015

Publication series

Name	European Solid-State Device Research Conference
Volume	2015-November
ISSN (Print)	1930-8876

Conference

Conference	45th European Solid-State Device Research Conference, ESSDERC 2015
Country/Territory	Austria
City	Graz
Period	14/09/15 → 18/09/15

Keywords

Aging
Degradation
Integrated circuit modeling
MOS devices
Semiconductor process modeling
Threshold voltage
Transistors

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10.1109/ESSDERC.2015.7324758

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Hussin, R., Gerrer, L., Ding, J., Wang, L., Amoroso, S. M., Cheng, B., Reid, D., Weckx, P., Simicic, M., Franco, J., Vanderheyden, A., Vanhaeren, D., Horiguchi, N., Kaczer, B., & Asenov, A. (2015). Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow. In T. Grasser, W. Pribyl, & M. Schrems (Eds.), ESSDERC 2015 - Proceedings of the 45th European Solid-State Device Research Conference (pp. 238-241). Article 7324758 (European Solid-State Device Research Conference; Vol. 2015-November). Editions Frontieres. https://doi.org/10.1109/ESSDERC.2015.7324758

Hussin, Razaidi ; Gerrer, Louis ; Ding, Jie et al. / Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow. ESSDERC 2015 - Proceedings of the 45th European Solid-State Device Research Conference. editor / Tibor Grasser ; Wolfgang Pribyl ; Martin Schrems. Editions Frontieres, 2015. pp. 238-241 (European Solid-State Device Research Conference).

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title = "Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow",

abstract = "This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time.",

keywords = "Aging, Degradation, Integrated circuit modeling, MOS devices, Semiconductor process modeling, Threshold voltage, Transistors",

author = "Razaidi Hussin and Louis Gerrer and Jie Ding and Liping Wang and Amoroso, {Salvatore M.} and Binjie Cheng and Dave Reid and Pieter Weckx and Marco Simicic and Jacopo Franco and Annelies Vanderheyden and Danielle Vanhaeren and Naoto Horiguchi and Ben Kaczer and Asen Asenov",

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doi = "10.1109/ESSDERC.2015.7324758",

language = "English",

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Hussin, R, Gerrer, L, Ding, J, Wang, L, Amoroso, SM, Cheng, B, Reid, D, Weckx, P, Simicic, M, Franco, J, Vanderheyden, A, Vanhaeren, D, Horiguchi, N, Kaczer, B & Asenov, A 2015, Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow. in T Grasser, W Pribyl & M Schrems (eds), ESSDERC 2015 - Proceedings of the 45th European Solid-State Device Research Conference., 7324758, European Solid-State Device Research Conference, vol. 2015-November, Editions Frontieres, pp. 238-241, 45th European Solid-State Device Research Conference, ESSDERC 2015, Graz, Austria, 14/09/15. https://doi.org/10.1109/ESSDERC.2015.7324758

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow. / Hussin, Razaidi; Gerrer, Louis; Ding, Jie et al.
ESSDERC 2015 - Proceedings of the 45th European Solid-State Device Research Conference. ed. / Tibor Grasser; Wolfgang Pribyl; Martin Schrems. Editions Frontieres, 2015. p. 238-241 7324758 (European Solid-State Device Research Conference; Vol. 2015-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hussin, Razaidi

AU - Gerrer, Louis

AU - Ding, Jie

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AU - Amoroso, Salvatore M.

AU - Cheng, Binjie

AU - Reid, Dave

AU - Weckx, Pieter

AU - Simicic, Marco

AU - Franco, Jacopo

AU - Vanderheyden, Annelies

AU - Vanhaeren, Danielle

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AB - This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time.

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KW - Integrated circuit modeling

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KW - Semiconductor process modeling

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Hussin R, Gerrer L, Ding J, Wang L, Amoroso SM, Cheng B et al. Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow. In Grasser T, Pribyl W, Schrems M, editors, ESSDERC 2015 - Proceedings of the 45th European Solid-State Device Research Conference. Editions Frontieres. 2015. p. 238-241. 7324758. (European Solid-State Device Research Conference). doi: 10.1109/ESSDERC.2015.7324758

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

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