Abstract
In recent years, with the development of Synthetic Aperture Radar (SAR) technology, the required resolution and imaging bandwidth for spaceborne SAR have been continuously increasing, posing stringent requirements on real-time imaging systems. To address the issue of uneven computing power allocation in implementing the Chirp Scaling (CS) algorithm on an FPGA+DSP platform, a spaceborne SAR imaging system with high-performance polynomial engines was designed, which enables the mapping of the Taylor series-based Chirp Scaling algorithm onto a hardware platform. The system is implemented using Xilinx's XC7VX690T FPGA and TI's TMS320C6678 DSP. The high-performance polynomial engine is designed with a parallel pipeline structure, supporting computation of polynomial up to seventh order. It offers flexible configuration and high versatility. The spaceborne SAR imaging system with high-performance polynomial engines can achieve SAR imaging in 16K×16K resolution with a time of 15.64 seconds, meeting the requirements of real-time SAR imaging applications in large-scale data scenarios.
Original language | English |
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Pages (from-to) | 2435-2442 |
Number of pages | 8 |
Journal | IET Conference Proceedings |
Volume | 2023 |
Issue number | 47 |
DOIs | |
Publication status | Published - 2023 |
Event | IET International Radar Conference 2023, IRC 2023 - Chongqing, China Duration: 3 Dec 2023 → 5 Dec 2023 |
Keywords
- CSA
- DSP
- FPGA
- POLYNOMIAL ENGINE
- SPACEBORNE SAR