TY - GEN
T1 - Simulation study of IGZO (with CuOx)/Si Complementary Ferroelectric FET (CFeFET) for Multi-bit Content Addressable Memory
AU - Guo, Zhijian
AU - Yang, Guanhua
AU - Mo, Fei
AU - Wang, Yeliang
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - In this work, we proposed and studied a novel complementary ferroelectric field-effect transistor (CFeFET) using n-type IGZO channel with CuOx insertion layer and p-type silicon channel by TCAD simulations. The TCAD simulation of ultra-compact multi-bit Content Addressable Memory (CAM) design based on an IGZO/Si CFeFET is studied for the first time. The proposed design overcomes the mismatch in memory window (MW) between IGZO-FeFET and Si-FeFET caused by the lack of hole carriers in IGZO-FeFET during erase operation. The 1-bit and multi-bit CAM cell operation are successfully achieved through multi-level cell (MLC) operation of CFeFET with single IGZO-FeFET and Si-FeFET, showing great potential for advanced and high-density non-volatile memory applications.
AB - In this work, we proposed and studied a novel complementary ferroelectric field-effect transistor (CFeFET) using n-type IGZO channel with CuOx insertion layer and p-type silicon channel by TCAD simulations. The TCAD simulation of ultra-compact multi-bit Content Addressable Memory (CAM) design based on an IGZO/Si CFeFET is studied for the first time. The proposed design overcomes the mismatch in memory window (MW) between IGZO-FeFET and Si-FeFET caused by the lack of hole carriers in IGZO-FeFET during erase operation. The 1-bit and multi-bit CAM cell operation are successfully achieved through multi-level cell (MLC) operation of CFeFET with single IGZO-FeFET and Si-FeFET, showing great potential for advanced and high-density non-volatile memory applications.
KW - Complementary Ferroelectric FET (CFeFET)
KW - Content Addressable Memory (CAM)
KW - IGZO-FeFET
KW - Multi-Level Cell (MLC)
UR - https://www.scopus.com/pages/publications/105040815001
U2 - 10.1109/EDTM65772.2026.11497553
DO - 10.1109/EDTM65772.2026.11497553
M3 - Conference contribution
AN - SCOPUS:105040815001
T3 - 10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026
BT - 10th IEEE Electron Devices Technology and Manufacturing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026
Y2 - 1 March 2026 through 4 March 2026
ER -