RocketTC: A high throughput traffic classification architecture on FPGA

Deep packet inspection (DPI) based traffic classification methods could achieve more than 95% accuracy and recognition rate. However, due to considerable computation and storage expenditures, existing software-based solutions could not offer sufficient processing capability for widely deployed high speed networks and massive concurrent flows. This paper proposes RocketTC, a high performance FPGA-based architecture for traffic classification with optimized DPI method, flexible and scalable classification engines and flow management scheme. Specifically, RocketTC architecture introduces two key elements to achieve high performance: an efficient flow management scheme using only on-chip BRAMs for storing the flow table, and a parallel and pipelined classification engine array supporting partial dynamic reconfiguration (PDR). We implemented RocketTC on a Virtex-5 FPGA based platform to evaluate its actual performance. Experimental results show that the prototype could offer a sustained throughput of over 20 Gbps and achieve high accuracy above 97% for classifying 92 popular applications while regarding L7-filter as the ground truth. Additionally, it is easy for RocketTC to update for the purpose of classifying more applications.