Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic

Alekhya Yalla; Umakanta Nanda; Chandan Kumar Pandey; Shujun Ye

doi:10.1109/AISP57993.2023.10134833

Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic

Alekhya Yalla^*
, Umakanta Nanda
, Chandan Kumar Pandey
, Shujun Ye

^*Corresponding author for this work

VIT-AP University
Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

In this work, Energy efficient Binary content addressable memory (BiCAM) is designed using reversible logic which is in high demand in fields of quantum computing, nano technology, data centric computing, software-defined networks and wide variety of high speed applications. BiCAM performs search operation in a single clock cycle. Binary content addressable memory (BiCAM) design based on reversible logic reduces power dissipation. Due to minimum heat dissipation, Reversible logic has gained its interest in recent years. A novel design of BiCAM array using reversible logic gates with transmission gate logic improves speed and reversibility ensures low power. The proposed reversible logic based 4x3 BiCAM array using transmission gates is implemented using mentor graphics at 130nm technology with Vdd=1.2V shows 95.2% efficiency in power compared to CMOS based BiCAM design. All reversible logic gates used in BiCAM design as analysed using transmission gate logic and compared with conventional gates.

Original language	English
Title of host publication	2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350320749
DOIs	https://doi.org/10.1109/AISP57993.2023.10134833
Publication status	Published - 2023
Externally published	Yes
Event	3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023 - Vijayawada, India Duration: 18 Mar 2023 → 20 Mar 2023

Publication series

Name	2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023

Conference

Conference	3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023
Country/Territory	India
City	Vijayawada
Period	18/03/23 → 20/03/23

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

BiCAM
Low power
Quantum cost
Reversible logic
SRAM
energy efficiency

Access to Document

10.1109/AISP57993.2023.10134833

Cite this

Yalla, A., Nanda, U., Pandey, C. K., & Ye, S. (2023). Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic. In 2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023 (2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/AISP57993.2023.10134833

Yalla, Alekhya ; Nanda, Umakanta ; Pandey, Chandan Kumar et al. / Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic. 2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023).

@inproceedings{25b9a4be021c48be92a708cf8e32b6c0,

title = "Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic",

abstract = "In this work, Energy efficient Binary content addressable memory (BiCAM) is designed using reversible logic which is in high demand in fields of quantum computing, nano technology, data centric computing, software-defined networks and wide variety of high speed applications. BiCAM performs search operation in a single clock cycle. Binary content addressable memory (BiCAM) design based on reversible logic reduces power dissipation. Due to minimum heat dissipation, Reversible logic has gained its interest in recent years. A novel design of BiCAM array using reversible logic gates with transmission gate logic improves speed and reversibility ensures low power. The proposed reversible logic based 4x3 BiCAM array using transmission gates is implemented using mentor graphics at 130nm technology with Vdd=1.2V shows 95.2\% efficiency in power compared to CMOS based BiCAM design. All reversible logic gates used in BiCAM design as analysed using transmission gate logic and compared with conventional gates.",

keywords = "BiCAM, Low power, Quantum cost, Reversible logic, SRAM, energy efficiency",

author = "Alekhya Yalla and Umakanta Nanda and Pandey, \{Chandan Kumar\} and Shujun Ye",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023 ; Conference date: 18-03-2023 Through 20-03-2023",

year = "2023",

doi = "10.1109/AISP57993.2023.10134833",

language = "English",

series = "2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023",

address = "United States",

}

Yalla, A, Nanda, U, Pandey, CK & Ye, S 2023, Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic. in 2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023. 2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023, Institute of Electrical and Electronics Engineers Inc., 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023, Vijayawada, India, 18/03/23. https://doi.org/10.1109/AISP57993.2023.10134833

Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic. / Yalla, Alekhya; Nanda, Umakanta; Pandey, Chandan Kumar et al.
2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic

AU - Yalla, Alekhya

AU - Nanda, Umakanta

AU - Pandey, Chandan Kumar

AU - Ye, Shujun

PY - 2023

Y1 - 2023

N2 - In this work, Energy efficient Binary content addressable memory (BiCAM) is designed using reversible logic which is in high demand in fields of quantum computing, nano technology, data centric computing, software-defined networks and wide variety of high speed applications. BiCAM performs search operation in a single clock cycle. Binary content addressable memory (BiCAM) design based on reversible logic reduces power dissipation. Due to minimum heat dissipation, Reversible logic has gained its interest in recent years. A novel design of BiCAM array using reversible logic gates with transmission gate logic improves speed and reversibility ensures low power. The proposed reversible logic based 4x3 BiCAM array using transmission gates is implemented using mentor graphics at 130nm technology with Vdd=1.2V shows 95.2% efficiency in power compared to CMOS based BiCAM design. All reversible logic gates used in BiCAM design as analysed using transmission gate logic and compared with conventional gates.

AB - In this work, Energy efficient Binary content addressable memory (BiCAM) is designed using reversible logic which is in high demand in fields of quantum computing, nano technology, data centric computing, software-defined networks and wide variety of high speed applications. BiCAM performs search operation in a single clock cycle. Binary content addressable memory (BiCAM) design based on reversible logic reduces power dissipation. Due to minimum heat dissipation, Reversible logic has gained its interest in recent years. A novel design of BiCAM array using reversible logic gates with transmission gate logic improves speed and reversibility ensures low power. The proposed reversible logic based 4x3 BiCAM array using transmission gates is implemented using mentor graphics at 130nm technology with Vdd=1.2V shows 95.2% efficiency in power compared to CMOS based BiCAM design. All reversible logic gates used in BiCAM design as analysed using transmission gate logic and compared with conventional gates.

KW - BiCAM

KW - Low power

KW - Quantum cost

KW - Reversible logic

KW - SRAM

KW - energy efficiency

UR - https://www.scopus.com/pages/publications/85163153622

U2 - 10.1109/AISP57993.2023.10134833

DO - 10.1109/AISP57993.2023.10134833

M3 - Conference contribution

AN - SCOPUS:85163153622

T3 - 2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023

BT - 2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023

Y2 - 18 March 2023 through 20 March 2023

ER -

Yalla A, Nanda U, Pandey CK, Ye S. Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic. In 2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 3rd International Conference on Artificial Intelligence and Signal Processing, AISP 2023). doi: 10.1109/AISP57993.2023.10134833

Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

Other files and links

Fingerprint

Cite this