Research on UWB synchronization technology and its implementation in FPGA

In order to simplify the complexity and reduce clock of field programmable gate array(FPGA), an improved multi-channel parallel synchronization scheme was proposed based on traditional sliding window correlation, combining the 1 bit quantification and multipath energy accumulation algorithm. In this paper, a method was designed to implement the FPGA, the influence of 1 bit quantification on system performance was analyzed and the quantitative results of SNR loss was provided. The simulation results show that the 1 bit quantification can bring 2 dB SNR loss in Gaussian and Rayleigh channel. The best threshold range can be got through the simulation of false alarm probability and detection probability in Gaussian and Rayleigh channel.