TY - JOUR
T1 - Research on a Method of Realizing High Performance Ultra-Long Pulse Compression Processor Based on FPGA
AU - Wu, Hong Hao
AU - Qiao, Ting Ting
AU - Chen, He
AU - Xie, Yi Zhuang
AU - Li, Yong Rui
N1 - Publisher Copyright:
© The Institution of Engineering & Technology 2023.
PY - 2023
Y1 - 2023
N2 - Pulse compression plays a vital role in radar signal processing. With the rapid development of synthetic aperture radar (SAR) imaging technology, the demand for spaceborne SAR imaging processing is becoming more and more urgent, especially the need to support the real-time application of ultra-long pulse compression accelerators. However, limited on-chip resources and memory access bandwidth have always been key bottlenecks restricting the design of ultra-long pulse compression processing. FPGA is widely regarded as a processor that is both highly parallelized and has excellent computing speed. Therefore, this research is committed to proposing a new processor design method based on FPGA to cope with ultra-long point pulse compression processing. First, to be able to effectively handle ultra-long sequence pulse compression up to 1M points, we propose an architecture with careful optimization. Secondly, in order to improve processing efficiency and reduce resource overhead, we propose a fixed-point data fitting implementation strategy. Finally, this study also explores an on-chip storage optimization method for reference function spectrum for linear frequency modulation (LFM) signals, which not only effectively reduces the cost of on-chip resources, but also saves storage transmission bandwidth. These innovative designs and optimization strategies will provide strong support for further development in the field of ultra-long-point pulse compression processing.
AB - Pulse compression plays a vital role in radar signal processing. With the rapid development of synthetic aperture radar (SAR) imaging technology, the demand for spaceborne SAR imaging processing is becoming more and more urgent, especially the need to support the real-time application of ultra-long pulse compression accelerators. However, limited on-chip resources and memory access bandwidth have always been key bottlenecks restricting the design of ultra-long pulse compression processing. FPGA is widely regarded as a processor that is both highly parallelized and has excellent computing speed. Therefore, this research is committed to proposing a new processor design method based on FPGA to cope with ultra-long point pulse compression processing. First, to be able to effectively handle ultra-long sequence pulse compression up to 1M points, we propose an architecture with careful optimization. Secondly, in order to improve processing efficiency and reduce resource overhead, we propose a fixed-point data fitting implementation strategy. Finally, this study also explores an on-chip storage optimization method for reference function spectrum for linear frequency modulation (LFM) signals, which not only effectively reduces the cost of on-chip resources, but also saves storage transmission bandwidth. These innovative designs and optimization strategies will provide strong support for further development in the field of ultra-long-point pulse compression processing.
KW - 2D FFT
KW - FPGA
KW - Pulse compression processor
KW - Ultra-Long points
UR - http://www.scopus.com/inward/record.url?scp=85203131220&partnerID=8YFLogxK
U2 - 10.1049/icp.2024.1456
DO - 10.1049/icp.2024.1456
M3 - Conference article
AN - SCOPUS:85203131220
SN - 2732-4494
VL - 2023
SP - 2370
EP - 2374
JO - IET Conference Proceedings
JF - IET Conference Proceedings
IS - 47
T2 - IET International Radar Conference 2023, IRC 2023
Y2 - 3 December 2023 through 5 December 2023
ER -