Recursive and folded implementation of digital matched filter

An optimized structure of FPGA realization for digital matched filters (DMF) is presented. By fully applying the storage potential of 16 bit shift register LUT (SRL16E), a recursive delay line (RDL) is proposed with the characters of multiplicative decrease of taps number and increase of taps' sample rate. Recursive folded DMF based on RDL and time-division multiplexing is also analyzed. By using the optimized structure, the sample rate of delay line and the throughput of correlation-calculation unit (CCU) are both increased, and the resource consumption of DMF is decreased greatly at the price of increasing clock frequency. The resource consumption of 1/4 recursive folded structure of DMF is only 1/3 of the consumption of unoptimized structure.