@inproceedings{af246daacfb84e61b2549ebb21b8f2c6,
title = "Receiver System Design for Universal Polyphase DFT Digital Channelization Algorithm",
abstract = "Receiver plays a vital role in various electronic countermeasure systems and has always been a hot topic to research. Based on the traditional receiver digital channelization structure, this paper further researches and derives the high-efficiency digital channelization structure based on polyphase discrete Fourier transform corresponding to various application scenarios. Then we design a 256-sub-channel digital channelization system and implement it on a 64-channel parallel digital down converter to verify the structure. The system design relies on system on chip as the platform, and we verify the feasibility of it on field programmable gate array.",
keywords = "Digital channelization, FPGA, multichannel digital down converter, polyphase filter, SoC",
author = "Shihang Lu and Zhengyu Su and Kaisheng Liao and Chao Li and Zhuoling Xiao and Bo Yan and Shuisheng Lin and Bo Wu",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 5th IEEE International Conference on Electronics Technology, ICET 2022 ; Conference date: 13-05-2022 Through 16-05-2022",
year = "2022",
doi = "10.1109/ICET55676.2022.9825105",
language = "English",
series = "2022 IEEE 5th International Conference on Electronics Technology, ICET 2022",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "867--873",
booktitle = "2022 IEEE 5th International Conference on Electronics Technology, ICET 2022",
address = "United States",
}